1. Field of the Invention
The present invention relates to a sense amplifier for a read only memory (ROM), and more particularly to an asynchronous sense amplifier.
2. Description of the Related Art
For highly integrated systems, a high speed ROM is required for any system with a high speed CPU. It is common practice that an instruction code is able to be read from a program ROM and executed within the same cycle. In other words, the access time of a program ROM should be less than half of one instruction cycle. For example, if a CPU is running at 100 MHz, the access time should be less than 5 ns.
FIG. 1 depicts a sense amplifier disclosed in U.S. Pat. No. 6,519,197. The sense amplifier 10 uses two pre-charge clocks phi1 and phi2, which reflects that the sense amplifier 10 is a synchronous circuit. Generally, synchronous sense amplifiers or synchronous ROM are more complicated and slower than asynchronous ones. For example, a synchronous sense amplifier needs a pre-charge period, but an asynchronous sense amplifier does not. Also, a synchronous sense amplifier needs a timing circuit to generate a pre-charge pulse, which occupies more chip area, but an asynchronous sense amplifier does not.
FIG. 2 depicts a sense amplifier disclosed in U.S. Pat. No. 7,126,869. The sense amplifier 20 includes a positive feedback with an inverter 21 and P channel transistors 22, 23. Also, a clock signal BPCHG acts as a pre-charge signal of a bit line. Apparently, this sense amplifier 20 is still a synchronous circuit, which possesses the same drawbacks as the structure in FIG. 1.